0.0* micron *-layer low-k process 2** million transistors
模具尺寸
33*mm2
数据位宽
*4 bit
CPU核心数
2
线程数
2
浮点单元
Integrated
1级缓存大小
2 x *4 KB 4-way set associative instruction caches 2 x *4 KB 4-way set associative write-through data caches 2 x 2 KB 4-way set associative prefetch caches 2 x 2 KB fully associative write caches
2级缓存大小
Shared 2 MB 4-way set associative cache
Physical memory
32 GB
多重处理
Up to 4 processors
特征
Visual Instruction Set 2.0
集成外设/组件
集成显卡
None
Other peripherals
SDRAM memory controller
L3 cache controller
电/热参数
Notes on Sun Microsystems UltraSparc IV+ 2.1 GHz
Binary compatible with other Sparc processors
L3 cache controller supports external 32 MB external 4-way set associative cache, shared by both cores
L2 cache operates at half of the processor frequency